On June 25, 2026, IBM announced what it called the world’s first sub-1nm chip: a working test chip built at a 7 angstrom, or 0.7 nanometer, node. The headline number is eye-catching, and it traveled fast. But the number is also the least interesting part of the announcement. The real breakthrough is the architecture underneath it, which IBM calls the nanostack, and understanding that difference is the key to reading this news accurately.
The short version: IBM did not shrink a transistor below one nanometer in any literal sense. It stacked two transistors vertically, in a way that roughly doubles the density of its 2nm technology and, IBM says, delivers up to 50 percent more performance or up to 70 percent better energy efficiency. That is a genuine advance, and it suggests the semiconductor roadmap has at least another decade of scaling left. It is also a research demonstration, not a product. Mass production is estimated to be around five years out, IBM has not said how it will be commercialized, and no one will be buying a sub-1nm chip any time soon. This piece explains what IBM actually built, why the nanostack is the story, why "sub-1nm" is a label rather than a measurement, and what it does and does not mean for the AI hardware that runs today’s models.
What IBM actually announced
IBM’s research division demonstrated a functioning chip at a 0.7nm node with nearly 100 billion transistors on a piece of silicon the size of a human fingernail. That is roughly twice the transistor density of IBM’s 2nm nanosheet technology, which the company first unveiled in 2021. Alongside the density gain, IBM reported up to 50 percent higher performance at the same power, or up to 70 percent lower power at the same performance, compared with its 2nm node, plus a 40 percent improvement in SRAM scaling, the on-chip memory that has been one of the hardest things to keep shrinking.
Crucially, this came out of IBM Research, not an IBM product line. IBM does not manufacture leading-edge chips for sale. It develops process technology and licenses it to the companies that do, which is why its 2nm nanosheet work now underpins mass-production efforts at Intel, Samsung, and TSMC, and why its Japanese manufacturing partner Rapidus is targeting 2nm production at scale in the second half of 2027. The sub-1nm chip is the next research milestone in that pipeline, not something IBM is about to ship.
The real breakthrough: the nanostack
For years, progress in chipmaking meant making transistors smaller. That approach has been running out of room, because at these scales the physics stops cooperating and features are only a handful of atoms wide. IBM’s nanostack changes the direction of travel: instead of shrinking transistors, it stacks them vertically.
A nanostack, in IBM’s design, places two transistors in two nanosheets built directly on top of one another. Each nanosheet is about 5nm tall, roughly the height of 15 silicon atoms, and the two sheets sit about 9nm apart. By building up rather than only out, IBM roughly doubles how many transistors fit in the same footprint without needing to shrink each one into physically impossible territory. This is the same conceptual move that let storage keep growing after planar limits were hit: when you cannot go smaller, go vertical.
That is why the industry commentary has coalesced around a clear message: look past the 0.7nm label, because the nanostack architecture is the actual advance. The vertical-stacking approach is what unlocks the density and efficiency gains, and it is the part with a decade of roadmap behind it.
Why "sub-1nm" is a label, not a measurement
It helps to be honest about what node names mean in 2026, because "sub-1nm" invites a misreading. Process node names like 2nm, 0.7nm, or Intel’s 18A stopped corresponding to any physical dimension of a transistor years ago. Nothing on a modern "2nm" chip is actually 2nm wide. The names are marketing-adjacent labels for a generation of technology, benchmarked against the density and performance a given node delivers, not a ruler measurement of a feature.
So IBM’s "sub-1nm" is best read as "the generation beyond 2nm," defined by the density and efficiency it achieves through the nanostack, rather than a claim that anything on the chip measures less than a nanometer. This is not IBM being dishonest; it is how the whole industry names nodes. But it is exactly why the density and efficiency figures, and the architecture that produces them, matter more than the headline number. When you see a sub-1nm or angstrom-era claim, the useful questions are how dense, how efficient, and how it was achieved, not what the node is called.
What it means for performance and AI
The gains IBM reports map directly onto what modern AI hardware needs. More transistors in the same area means more compute and more on-chip memory per chip. Better energy efficiency means more of that compute per watt, which is the binding constraint for data centers running large models and for the edge devices trying to run smaller ones. The 40 percent SRAM scaling matters here too, because on-chip memory bandwidth is often what starves an AI accelerator, and SRAM has been notoriously resistant to further shrinking.
If the nanostack scales as IBM projects, the practical payoff a decade out is chips that pack more capability into the same power envelope, which is the entire game for AI infrastructure. For a sense of how much that constraint shapes the current hardware market, our look at the hardware behind AI agents covers why memory and efficiency, not raw core counts, increasingly decide what you can actually run.
The caution is that none of this changes anything you can buy today. The chips training and serving today’s models are on 3nm and early 2nm processes. The nanostack is a signal about the trajectory, not a component in this year’s server.
The reality check: timeline and commercialization
This is the part most of the excited coverage underplays. IBM’s sub-1nm chip is a lab demonstration. The company estimates mass production is roughly five years away, it has not disclosed how it will commercialize the nanostack, and it has said its near-term focus is helping partners scale today’s 2nm nanosheet technology rather than pushing sub-1nm toward a fab.
Five years is a long time in this industry, and research milestones do not always translate cleanly into production. Yield, cost, and manufacturability are separate mountains from a working test chip, and plenty of promising architectures have stalled between the lab and the fab. The honest framing is the one IBM itself gestures at: this is a demonstration that the road ahead is open, evidence that scaling can continue past 2nm, rather than a product roadmap you can plan a purchase around.
Where it sits in the angstrom-era race
IBM’s announcement lands in the middle of an industry-wide push into what marketers have branded the angstrom era, with Intel, Samsung, and TSMC all racing through 2nm and toward their own sub-2nm and angstrom-labeled nodes. IBM’s role in that race is distinctive: it is the research house whose nanosheet architecture the big three foundries are already mass-producing. So a sub-1nm demonstration from IBM is less a competitor to those foundries and more a preview of the technology they may license and manufacture years from now.
That licensing model is why IBM’s research announcements carry weight beyond IBM. When the company that developed the architecture behind today’s leading-edge chips shows the next architecture working in the lab, it is a credible signal about where the whole industry can go, even if IBM never puts a sub-1nm chip on a shelf itself.
What it means for you
For anyone building on or buying AI hardware, the practical takeaway is measured. Nothing about your near-term decisions changes: the chips you can actually deploy are on today’s nodes, and will be for years. What IBM’s nanostack offers is confidence that the efficiency and density improvements the AI industry depends on are not about to hit a wall, which matters for long-range planning, capacity forecasting, and the broader question of whether compute will keep getting cheaper per unit of capability.
Read it as good news about the trajectory, delivered with a five-year horizon and the usual gap between a research demo and a shipping product. The nanostack is the real story, the 0.7nm is a label, and the road past 2nm now looks open in a way it did not a week ago.
Frequently Asked Questions
What did IBM announce?
On June 25, 2026, IBM Research demonstrated the world’s first sub-1nm chip: a working test chip at a 7 angstrom (0.7nm) node with nearly 100 billion transistors on a fingernail-sized piece of silicon. It uses a new nanostack architecture and delivers roughly twice the transistor density of IBM’s 2nm technology, with up to 50 percent more performance or up to 70 percent better energy efficiency.
What is the nanostack architecture?
The nanostack stacks transistors vertically instead of shrinking them. IBM’s design places two transistors in two nanosheets built on top of each other, each about 5nm tall (roughly 15 silicon atoms) and about 9nm apart. Building up rather than only out roughly doubles density without requiring each transistor to shrink into physically impossible dimensions. Most analysts consider the nanostack, not the 0.7nm label, the real breakthrough.
Is anything on the chip actually smaller than 1 nanometer?
No. Modern process node names like 2nm or 0.7nm stopped corresponding to any physical transistor dimension years ago; they are labels for a generation of technology defined by density and performance, not ruler measurements. IBM’s “sub-1nm” is best read as the generation beyond 2nm, achieved through the nanostack, rather than a claim that any feature measures under a nanometer.
When will sub-1nm chips be available to buy?
Not soon. IBM estimates mass production is roughly five years away, has not disclosed a commercialization path, and says its near-term focus is helping partners scale today’s 2nm technology. This is a research demonstration, not a product. Yield, cost, and manufacturability remain separate challenges from a working test chip.
Does IBM manufacture these chips?
No. IBM develops process technology and licenses it to the companies that manufacture leading-edge chips. Its 2nm nanosheet work already underpins mass-production efforts at Intel, Samsung, and TSMC, and its partner Rapidus targets 2nm production at scale in the second half of 2027. The sub-1nm chip is the next research milestone in that pipeline.
Why does this matter for AI?
AI hardware is constrained by compute per watt and on-chip memory bandwidth. More transistor density means more compute and memory per chip, better efficiency means more compute per watt, and IBM’s reported 40 percent SRAM scaling addresses a memory bottleneck that has been hard to move. If the nanostack scales as projected, it means the efficiency gains AI infrastructure depends on can continue past 2nm, though the payoff is a decade out.
How does this compare to Intel, Samsung, and TSMC?
Those three foundries are racing through 2nm and toward their own sub-2nm nodes, and all three are mass-producing chips based on nanosheet architecture IBM developed. IBM is the research house rather than a competing foundry, so a sub-1nm demonstration from IBM is best read as a preview of technology the big three may license and manufacture years from now, not a product competing with them today.
Is Moore’s Law dead?
IBM’s roadmap projects at least another decade of scaling on the strength of the nanostack, which is evidence that density and efficiency improvements can continue, even if the old pattern of simply shrinking transistors has run out of room. The direction has shifted from shrinking to stacking, but the practical goal, more capability in the same power envelope, is still advancing.
